1. Field of the Invention
The present invention relates to a flash memory cell, in particular, to a flash memory cell which can increase an operating speed and decrease a power consumption.
2. Brief Description of the Prior Art In general, the memory device such as a flash electrically erasable and programmable read only memory cell (EEPROM) has both functions of electrically programming and erasing, and is classified into a stack-gate type and split-gate type depending on the shape of a gate electrode thereof. Now, the structure and operation of conventional stack-gate type flash memory cell will be described below.
In the conventional stack-gate type flash memory cell, as shown in FIG. 1, a tunnel oxide film 2, a floating gate 3, a dielectric film 4 and a control gate 5 are sequentially stacked on a silicon substrate 1 to form a gate electrode G, and a source and drain regions 7 and 6 are formed in the silicon substrate 1 at both sides of the gate electrode G, respectively. The operation of programming and erasing of the flash memory cell as described above is as follows.
To program an information to the flash memory cell, that is, to charge the floating gate 3 with an electric charge, high voltage of +12 V is applied to the control gate 5, supply voltage of +5 V is applied to the drain region 6, and the ground voltage is applied to the source region 7 and the silicon substrate 1, respectively.
Then, a channel is formed in the silicon substrate 1 below the floating gate 3 due to the high voltage applied to the control gate 5, and the high electric field zone is formed in the silicon substrate 1 at the side of the drain region 6 due to the voltage applied to the drain region 6. At this time, a part of electrons existing in the channel receive the energy from the high electric field zone so as to be hot electrons, and a part of the hot electrons are injected to the floating gate 3 through the tunnel oxide film 2 by an electrical field formed in a vertical direction due to the high voltage applied to the control gate 5. Therefore, the threshold voltage (V.sub.T) of the flash memory cell rises due to the injection of the hot electron.
To erase the information programmed in the flash memory cell, that is, to discharge the electric charge stored in the floating gate 3, the ground voltage is applied to the control gate 5 and the silicon substrate 1, high voltage of +12V is applied to the source region 7, and the drain region 3 is floated. Then, the electrons injected into the floating gate 3 are moved to the source region 7 due to the F-N (fowler-nordheim) tunneling phenomenon, whereby the threshold voltage V.sub.T of the memory cell is lowered.
The conventional flash memory cell as described above has two gates (floating gate and control gate) formed of a polysilicon. Therefore, two insulating films, that is, the tunneling oxide film 2 and the dielectric film 4 are necessary to isolate between the silicon substrate 1 and the floating gate 3 and between the floating gate 3 and the control gate 5, respectively. However, in the process of forming the insulating films, it is difficult to control precisely a characteristic of the insulating films and to form the insulating films having a high reliability. In addition, a negative charge pump circuit must be comprised in the device to operate the memory cell, therefore, a high integration of the device is difficult. Furthermore, a power consumption increases due to the junction leakage.